The invention relates to semiconductor device fabrication and, more particularly, to techniques for capping interlevel dielectric (ILD) layers of interconnect structures such as damascene interconnect structures.
An integrated circuit (IC) device (also referred to as a semiconductor chip) can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate (wafer). For the IC device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of circuit elements are increased. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring (interconnect) structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors and other circuit elements on a complex IC.